The present invention relates to packaging of microelectronic devices, especially the packaging of semiconductor devices.
Certain types of microelectronic devices and semiconductor chips include devices such as acoustic transducers, radio frequency emitters and/or detectors and/or optoelectronic devices. Such devices typically require packaging which permits the passage of energy, e.g., acoustic, radio frequency or optical wavelength energy to and from devices at a face of a semiconductor chip.
Because such devices are often exposed at a front face of the microelectronic devices, they usually require protection from the elements, such as dust, other particles, contaminants and/or humidity. For this reason, it is advantageous to assemble the microelectronic device with a lid or other element covering the front face of such microelectronic device at an early stage of processing.
Other types of microelectronic devices require ease of testing. These goals are furthered in some packaged semiconductor chips and modules incorporating chips through use of a compliant pin-grid array or compliant ball-grid array (“BGA”) external interface. Compliant pin-grid array interfaces allow chips, especially for certain types of devices such as dynamic random access memories (“DRAMs”) to be temporarily connected to inexpensive fixtures for a variety of post-production testing, including burn-in tests and thermal stress tests. After such testing, the pin grid array interface allows the chip to be removed from the fixture and then installed more permanently in a final system.
For high speed performance, some types of chip packages incorporate controlled impedance transmission lines between contacts of the semiconductor chips and the external contacts of the package. It is particularly important to control the impedance seen by the wiring in a package where distances between pads of the chip and the external contacts of the package are long.
Certain types of mass-produced chips such as DRAMs also require packaging costs to be tightly controlled. Processing used to package such semiconductor chips can be performed on many chips simultaneously while the chips remain attached to each other in form of a wafer or portion of a wafer. Such “wafer-level” processing typically is performed by a sequence of processes applied to an entire wafer, after which the wafer is diced into individual chips. Advantageously, wafer-level packaging processes produce packaged chips which have the same area dimensions as the original semiconductor chips, making their interconnection compact on circuit panels and the like.
Heretofore, wafer-level packaging processes have not been available for fabricating chips having pin-grid array interfaces or compliant ball-grid array (“BGA”) interfaces which keep costs low while also incorporating controlled impedance transmission lines for high-speed performance.